1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, the invention relates to an arrangement of a differential amplifier circuit of a semiconductor device and a system of its operation.
2. Description of the Related Art
The following is a list of references referred in this specification. The references should be referred by reference numbers: Reference 1: JP-A No. 146177/1990; Reference 2: U.S. Pat. No. 5,412,605.
Reference 1 discloses a transfer gate (TG) clocking system with restore assist to improve restore operation of the TG clocking system and allow it to perform high speed amplification of data lines in a sense amplifier by separating the data line in the sense amplifier from the data line on the memory array side for a given period of time in the early stage of sense operation. The data lines on the array side are amplified according to the voltage of the data lines on the sense amplifier side at the same time as the data lines on the sense amplifier side are amplified.
Reference 2 discloses an overdrive system to improve transistor driving power at low voltage. According to this system, a voltage higher than final amplitude voltage is applied on source nodes of a CMOS sense amplifier for a given period of time in the early stage of sense operation.
In a dynamic random access memory (DRAM), a circuit (sense amplifier) for amplifying micro voltage difference, xcex94 V, between data line pairs generated by read-out operation to data line amplitude is connected to each of the data line pairs. Normally, as the sense amplifier, a cross couple type differential amplifier circuit comprising two transistors with different polarities is used. For instance, when a cross couple type differential amplifier circuit comprising a metal insulating film semiconductor or a metal oxide semiconductor (MOS) is used as the sense amplifier, N-type MOS (NMOS) and P-type MOS (PMOS) transistors are connected in series between the data lines respectively, and a source is commonly used for NMOS transistors and PMOS transistors. The gate is connected to a data line different from that of the drain.
In the sense amplifier, positive feedback amplification is performed according to the micro potential difference generated by the data read out from the memory cell selected by a word line, and one of the data line pairs is amplified to low level, and the other is amplified to high level. However, in DRAMs, a half-precharge system is typically used, which precharges the data line to one-half of amplitude voltage. During activation of the sense amplifier, only about xc2xd of the power source amplitude is applied between source and drain and between gate and source of the transistors. For this reason, compared with the peripheral circuit, operating speed is rapidly decreased when power source voltage is decreased. Also, there is a problem in the increase of the operating current when the sense amplifier is operated. When the number of the sense amplifiers operated at the same time is increased, voltage drop at the power source wiring that supplies power to the sense amplifier is increased. As a result, the voltage applied on the sense amplifier is decreased, and the operating speed is decreased further.
In DRAMs, it is desirable to achieve low power consumption, low voltage, and high-speed operation. In particular, it is desirable to reduce access time, i.e., the time from the command input to the output of data, and also to decrease the cycle time to determine random access time. When the sense speed is decreased due to low voltage, more time is required to output the data to outside from the sense amplifier, and this leads to the increase of access time. Further, in DRAM, it is necessary to rewrite (restore) the data once read out to the memory cell for destructive read-out. This restore operation may be slower compared with the sense operation, while high-speed operation is desirable to determine the cycle time of the DRAM. When it is turned to low voltage, charge/discharge operation of the data line is delayed. This results in the increase of the restore time, in the increase of cycle time, and in the deterioration of random access performance characteristics. Therefore, to decrease access time and cycle time of DRAM during low voltage, it is essential to reduce the sense time and the restore time of the sense amplifier.
As the sense system at low voltage, the overdrive system of Reference 2 is known. At low voltage of 1 V, charge and discharge are performed at the same time on the data lines in the sense amplifier and in the array, and the restore time is extensively reduced, but the decrease of the sense time is not sufficient.
On the other hand, as a technique to decrease only the sense time, a TG clocking system is proposed. However, the restore operation is performed after amplification in the sense amplifier, and the restore time is increased. For this reason, a TG clocking system with restore assist by modifying the restore operation of TG clocking system of Reference 1 has been proposed. However, even in this system, it is difficult to achieve high-speed restore operation under low voltage. FIG. 19 represents the results of simulation, showing the relation between the restore time RSTIME (ns) required for writing up to 90% to the storage nodes of the memory cell and the array voltage VDL (V). Restore time of a TG clocking system and restore time of a conventional type TG clocking system with the conventional type restore assist are shown in (c) and (b) respectively. In the TG clocking system added with restore amplifier, the restore time of the xe2x80x98Hxe2x80x99 side data to the memory cell is rapidly increased when it is turned to low voltage. In particular, when the array voltage VDL is 1.2 V or less, the restore time exceeds 25 ns, and the cycle time of the array is greater than 55 ns. This is because the restore amplifier and the sense amplifier are driven by the same power source. As a result, voltage drop occurs due to resistance of the power source wiring. Amplitude of the data line on the array side is decreased, and the charge stored in the memory cell is decreased. When the writing voltage of the data on the xe2x80x98Hxe2x80x99 side is decreased, data holding time is shortened, which is a problem specific to DRAM. If the refresh operation is frequently performed to compensate for this, power consumption is increased. Also, the amplitude of the power source used for the amplifying operation in the sense amplifier is decreased, and this leads to an increase in the access time. For this reason, it is desired to have a sense system where both high-speed sense operation and high-speed restore operation can be performed at the same time.
The present invention provides a sense amplifier arrangement where both a high-speed sense operation and a high-speed restore operation can be performed simultaneously in a DRAM operated at low voltage to achieve high-speed access and shorter cycle time.
In carrying out the invention, one preferred aspect resides in the constitution where the power source of the sense amplifier for external data output is separated from the power source of the restore amplifier to rewrite to the memory cell. This prevents the changes in the power source of the sense amplifier for external data output.
Another preferred aspect of the present invention resides in the constitution where the wiring on the array is utilized and the drivers are dispersedly arranged. This allows power source resistance of the restore amplifier to be decreased, and the restore time to be reduced by temporarily driving at high voltage.
Other and further objects, features and advantages of the invention will appear more fully from the following description.